MARC details
| 000 -LEADER |
|---|
| fixed length control field |
01169nam a22003134a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
BD-DhDIU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20250603111941.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
020510s2002 maua b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2002071439 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0072823151 (alk. paper) |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
DLC |
| -- |
BD-DhDIU |
| Language of cataloging |
ENG |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7868.L6 |
| Item number |
B76 2003 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.392/ B877f |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Brown, Stephen. |
| 9 (RLIN) |
6901 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Fundamentals of digital logic with Verilog design / |
| Statement of responsibility, etc |
Stephen Brown, Zvonko Vranesic. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
1st ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
New Delhi : |
| Name of publisher, distributor, etc |
Tata McGraw-Hill, |
| Date of publication, distribution, etc |
2006. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xx, 844 p. : |
| Other physical details |
ill., figs., tables ; |
| Dimensions |
24 cm. |
| 440 #0 - SERIES STATEMENT/ADDED ENTRY--TITLE |
|---|
| Title |
McGraw-Hill series in electrical and computer engineering |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 526 ## - STUDY PROGRAM INFORMATION NOTE |
|---|
| Program name |
CSE, ETE, EEE |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Logic circuits |
| General subdivision |
Design and construction |
| -- |
Data processing. |
| 9 (RLIN) |
6902 |
|
|---|
| Topical term or geographic name as entry element |
Verilog (Computer hardware description language) |
| 9 (RLIN) |
6903 |
|
|---|
| Topical term or geographic name as entry element |
Computer-aided design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Vranesic, Zvonko. |
| 9 (RLIN) |
6904 |
| 856 41 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Table of contents only |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/enhancements/fy0702/2002071439-t.html">http://www.loc.gov/catdir/enhancements/fy0702/2002071439-t.html</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Book |
| Koha issues (borrowed), all copies |
40 |