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CMOS circuit design, layout, and simulation / R. Jacob Baker, Harry W. Li, and David E. Boyce.

By: Contributor(s): Material type: TextTextSeries: IEEE Press series on microelectronic systemsPublication details: New Delhi : Prentice-Hall of India, 2005.Description: xxiv, 902 p. : ill., figs; 23 cmISBN:
  • 8120316827
Subject(s): DDC classification:
  • 621.3973/ B167c 22
LOC classification:
  • TK7871.99.M44 B35 1998
Contents:
Pt. I. CMOS Fundamentals. Ch. 1. Introduction. Ch. 2. The Well. Ch. 3. The Metal Layers. Ch. 4. The Active and Poly Layers. Ch. 5. The MOSFET. Ch. 6. The BSIM SPICE Model. Ch. 7. CMOS Passive Elements. Ch. 8. Design Verification with LASICKT. Ch. 9. Analog MOSFET Models. Ch. 10. The Digital Model -- Pt. II. CMOS Digital Circuits. Ch. 11. The Inverter. Ch. 12. Static Logic Gates. Ch. 13. The TG and Flip-Flops. Ch. 14. Dynamic Logic Gates. Ch. 15. VLSI Layout. Ch. 16. BiCMOS Logic Gates. Ch. 17. Memory Circuits. Ch. 18. Special-Purpose Digital Circuits. Ch. 19. Digital Phase-Locked Loops -- Pt. III. CMOS Analog Circuits. Ch. 20. Current Sources and Sinks. Ch. 21. References. Ch. 22. Amplifiers. Ch. 23. Feedback Amplifiers. Ch. 24. Differential Amplifiers. Ch. 25. Operational Amplifiers -- Pt. IV. Mixed-Signal Circuits. Ch. 26. Nonlinear Analog Circuits. Ch. 27. Dynamic Analog Circuits. Ch. 28. Data Converter Fundamentals.
Ch. 29. Data Converter Architectures. App. A. Orbit's CN20 Process -- App. B. MOSIS Scalable Design Rules -- App. C. HP's CMOS14TB.
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Holdings
Item type Current library Collection Call number Copy number Status Date due Barcode Item holds
Book Book Daffodil International University Library General Stacks Non-fiction 621.39732/ B167c (Browse shelf(Opens below)) 1 Available 010443
Book Book Daffodil International University Library General Stacks Non-fiction 621.39732/ B167c (Browse shelf(Opens below)) 2 Available 010444
Book Book Daffodil International University Library General Stacks Non-fiction 621.39732/ B167c (Browse shelf(Opens below)) 3 Available 010445
Total holds: 0

"IEEE Circuits & Systems Society, sponsor, IEEE Solid-State Circuits Society, sponsor."

Includes bibliographical references and index.

Pt. I. CMOS Fundamentals. Ch. 1. Introduction. Ch. 2. The Well. Ch. 3. The Metal Layers. Ch. 4. The Active and Poly Layers. Ch. 5. The MOSFET. Ch. 6. The BSIM SPICE Model. Ch. 7. CMOS Passive Elements. Ch. 8. Design Verification with LASICKT. Ch. 9. Analog MOSFET Models. Ch. 10. The Digital Model -- Pt. II. CMOS Digital Circuits. Ch. 11. The Inverter. Ch. 12. Static Logic Gates. Ch. 13. The TG and Flip-Flops. Ch. 14. Dynamic Logic Gates. Ch. 15. VLSI Layout. Ch. 16. BiCMOS Logic Gates. Ch. 17. Memory Circuits. Ch. 18. Special-Purpose Digital Circuits. Ch. 19. Digital Phase-Locked Loops -- Pt. III. CMOS Analog Circuits. Ch. 20. Current Sources and Sinks. Ch. 21. References. Ch. 22. Amplifiers. Ch. 23. Feedback Amplifiers. Ch. 24. Differential Amplifiers. Ch. 25. Operational Amplifiers -- Pt. IV. Mixed-Signal Circuits. Ch. 26. Nonlinear Analog Circuits. Ch. 27. Dynamic Analog Circuits. Ch. 28. Data Converter Fundamentals.

Ch. 29. Data Converter Architectures. App. A. Orbit's CN20 Process -- App. B. MOSIS Scalable Design Rules -- App. C. HP's CMOS14TB.

CSE, CIS, CS, ETE, EEE

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